Alliance Memory AS4C256M16D3LC Series SDRAM - DDR3L, AS4C256M16D3LC-10BAN, 4G, 256M x 16 bit, 800 MHz, 1.35 V, FBGA, 96 Pins, 209 per Tray

Product Description

• Double-data-rate architecture;two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipe lined architecture
• Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs;center-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge;data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted CAS by programmable additive latency for better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality:Synchronous ODTDynamic ODTAsynchronous ODTMulti Purpose Register (MPR) for pre-defined pattern read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• RESET pin for Power-up sequence and reset function
• SRT range : Normal/extended
• Programmable Output driver impedance control